1. Field of the Invention
The invention relates to an electronic clock technique. Particularly, the invention relates to an apparatus and a method for supplying clock adapted to an electronic clock system.
2. Description of Related Art
FIG. 1 is a schematic diagram of a conventional electronic clock system 100. Referring to FIG. 1, a general electronic device is configured with the electronic clock system 100, and the electronic clock system 100 provides a clock signal CLK required by the electronic device to ensure a normal operation of the electronic device. The electronic clock system 100 includes a frequency generation module 10, a phase locked loop (PLL) 20, a counter 30, a crystal oscillator 40 and a battery BAT. The electronic clock system 100 generates the clock system CLK of 32,768 Hz through the crystal oscillator 40 and the frequency generation module 10. The PLL 20 multiplies a frequency of the clock signal CLK and provides the same to a post circuit for utilization. The counter 30 uses the clock signal CLK to generate a date code.
A dot line LL′ in FIG. 1 divides the electronic clock system 100 into two regions according to different power usage statuses. The region located to the left of the dot line LL′ is always on, and even if the electronic device is power off, in order to display a correct date when the electronic clock system 100 is turned on next time, the region located to the left of the dot line LL′ is kept operating, so that the counter 30 continues to operate. Moreover, a status of the region located to the right of the dot line LL′ is determined according to the power usage status of the system, and such region is turned on when the system is power on, and is turned off when the system is power off. Therefore, when the system is power off, the frequency generation module 10 is still required to continually output the clock signal CLK to the counter 30, so that the power of the battery BAT is continuously consumed when the system is power off, which cannot be saved.
Generally, a dynamic power consumption P=(½)×(C×V2×f), where C, V and f respectively represent a capacitance, a voltage and a frequency, V2 represents a square of the voltage. In theory, if amplitude of the voltage is decreased, the value P is decreased, and the power is saved. However, if the amplitude of the voltage is decreased, an obvious disadvantage is that a noise increases, and the noise or jitter may cause an inaccurate duty cycle of the clock signal CLK. Therefore, under the structure of the conventional electronic clock system 100, in order to save power, the frequency-multiplication clock output by the PLL 20 can be abnormal.